DoxigAlpha
std › Build › Target › powerpc › cpu

cpu

= .{ .name = "440", .llvm_name = "440", .features = featureSet(&[_]Feature{ .fres, .frsqrte, .isel, .msync, }), }

Values

#
@"440"
= .{ .name = "440", .llvm_name = "440", .features = featureSet(&[_]Feature{ .fres, .frsqrte, .isel, .msync, }), }
@"450"
= .{ .name = "450", .llvm_name = "450", .features = featureSet(&[_]Feature{ .fres, .frsqrte, .isel, .msync, }), }
@"601"
= .{ .name = "601", .llvm_name = "601", .features = featureSet(&[_]Feature{ .fpu, }), }
@"602"
= .{ .name = "602", .llvm_name = "602", .features = featureSet(&[_]Feature{ .fpu, }), }
@"603"
= .{ .name = "603", .llvm_name = "603", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"603e"
= .{ .name = "603e", .llvm_name = "603e", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"603ev"
= .{ .name = "603ev", .llvm_name = "603ev", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"604"
= .{ .name = "604", .llvm_name = "604", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"604e"
= .{ .name = "604e", .llvm_name = "604e", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"620"
= .{ .name = "620", .llvm_name = "620", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"7400"
= .{ .name = "7400", .llvm_name = "7400", .features = featureSet(&[_]Feature{ .altivec, .fres, .frsqrte, }), }
@"7450"
= .{ .name = "7450", .llvm_name = "7450", .features = featureSet(&[_]Feature{ .altivec, .fres, .frsqrte, }), }
@"750"
= .{ .name = "750", .llvm_name = "750", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
@"970"
= .{ .name = "970", .llvm_name = "970", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fres, .frsqrte, .fsqrt, .mfocrf, .stfiwx, }), }
a2
= .{ .name = "a2", .llvm_name = "a2", .features = featureSet(&[_]Feature{ .@"64bit", .booke, .cmpb, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .recipprec, .slow_popcntd, .stfiwx, }), }
e500
= .{ .name = "e500", .llvm_name = "e500", .features = featureSet(&[_]Feature{ .isel, .msync, .spe, }), }
e500mc
= .{ .name = "e500mc", .llvm_name = "e500mc", .features = featureSet(&[_]Feature{ .booke, .isel, .stfiwx, }), }
e5500
= .{ .name = "e5500", .llvm_name = "e5500", .features = featureSet(&[_]Feature{ .@"64bit", .booke, .isel, .mfocrf, .stfiwx, }), }
future
= .{ .name = "future", .llvm_name = "future", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fast_MFLR, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .fuse_add_logical, .fuse_arith_add, .fuse_logical, .fuse_logical_add, .fuse_sha3, .fuse_store, .htm, .icbt, .isa_future_instructions, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .mma, .partword_atomics, .pcrelative_memops, .popcntd, .power10_vector, .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, }), }
g3
= .{ .name = "g3", .llvm_name = "g3", .features = featureSet(&[_]Feature{ .fres, .frsqrte, }), }
g4
= .{ .name = "g4", .llvm_name = "g4", .features = featureSet(&[_]Feature{ .altivec, .fres, .frsqrte, }), }
@"g4+"
= .{ .name = "g4+", .llvm_name = "g4+", .features = featureSet(&[_]Feature{ .altivec, .fres, .frsqrte, }), }
g5
= .{ .name = "g5", .llvm_name = "g5", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fres, .frsqrte, .fsqrt, .mfocrf, .stfiwx, }), }
generic
= .{ .name = "generic", .llvm_name = "generic", .features = featureSet(&[_]Feature{ .hard_float, }), }
ppc
= .{ .name = "ppc", .llvm_name = "ppc", .features = featureSet(&[_]Feature{ .hard_float, }), }
ppc64
= .{ .name = "ppc64", .llvm_name = "ppc64", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fres, .frsqrte, .fsqrt, .mfocrf, .stfiwx, }), }
ppc64le
= .{ .name = "ppc64le", .llvm_name = "ppc64le", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .fuse_addi_load, .fuse_addis_load, .htm, .icbt, .isa_v206_instructions, .isa_v207_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .partword_atomics, .popcntd, .power8_vector, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, }), }
pwr10
= .{ .name = "pwr10", .llvm_name = "pwr10", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fast_MFLR, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .fuse_add_logical, .fuse_arith_add, .fuse_logical, .fuse_logical_add, .fuse_sha3, .fuse_store, .htm, .icbt, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .mma, .partword_atomics, .pcrelative_memops, .popcntd, .power10_vector, .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, }), }
pwr11
= .{ .name = "pwr11", .llvm_name = "pwr11", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fast_MFLR, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .fuse_add_logical, .fuse_arith_add, .fuse_logical, .fuse_logical_add, .fuse_sha3, .fuse_store, .htm, .icbt, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .mma, .partword_atomics, .pcrelative_memops, .popcntd, .power10_vector, .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, }), }
pwr3
= .{ .name = "pwr3", .llvm_name = "pwr3", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fres, .frsqrte, .mfocrf, .stfiwx, }), }
pwr4
= .{ .name = "pwr4", .llvm_name = "pwr4", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fres, .frsqrte, .fsqrt, .mfocrf, .stfiwx, }), }
pwr5
= .{ .name = "pwr5", .llvm_name = "pwr5", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .mfocrf, .stfiwx, }), }
pwr5x
= .{ .name = "pwr5x", .llvm_name = "pwr5x", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .mfocrf, .stfiwx, }), }
pwr6
= .{ .name = "pwr6", .llvm_name = "pwr6", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .cmpb, .fcpsgn, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .lfiwax, .mfocrf, .recipprec, .stfiwx, }), }
pwr6x
= .{ .name = "pwr6x", .llvm_name = "pwr6x", .features = featureSet(&[_]Feature{ .@"64bit", .altivec, .cmpb, .fcpsgn, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .lfiwax, .mfocrf, .recipprec, .stfiwx, }), }
pwr7
= .{ .name = "pwr7", .llvm_name = "pwr7", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .extdiv, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .popcntd, .recipprec, .stfiwx, .two_const_nr, .vsx, }), }
pwr8
= .{ .name = "pwr8", .llvm_name = "pwr8", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .fuse_addi_load, .fuse_addis_load, .htm, .icbt, .isa_v206_instructions, .isa_v207_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .partword_atomics, .popcntd, .power8_vector, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, }), }
pwr9
= .{ .name = "pwr9", .llvm_name = "pwr9", .features = featureSet(&[_]Feature{ .@"64bit", .allow_unaligned_fp_access, .bpermd, .cmpb, .crbits, .crypto, .direct_move, .extdiv, .fcpsgn, .fpcvt, .fprnd, .fre, .fres, .frsqrte, .frsqrtes, .fsqrt, .htm, .icbt, .isa_v206_instructions, .isel, .ldbrx, .lfiwax, .mfocrf, .partword_atomics, .popcntd, .power9_vector, .ppc_postra_sched, .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, .vectors_use_two_units, }), }