cpu
= .{ .name = "baseline_rv32", .llvm_name = null, .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .d, .i, .m, }), }
Values
- baseline_rv32
- = .{ .name = "baseline_rv32", .llvm_name = null, .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .d, .i, .m, }), }
- baseline_rv64
- = .{ .name = "baseline_rv64", .llvm_name = null, .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, }), }
- generic
- = .{ .name = "generic", .llvm_name = "generic", .features = featureSet(&[_]Feature{}), }
- generic_rv32
- = .{ .name = "generic_rv32", .llvm_name = "generic-rv32", .features = featureSet(&[_]Feature{ .@"32bit", .i, .optimized_nf2_segment_load_store, }), }
- generic_rv64
- = .{ .name = "generic_rv64", .llvm_name = "generic-rv64", .features = featureSet(&[_]Feature{ .@"64bit", .i, .optimized_nf2_segment_load_store, }), }
- mips_p8700
- = .{ .name = "mips_p8700", .llvm_name = "mips-p8700", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .mips_p8700, .xmipscmove, .xmipslsp, .zba, .zbb, .zifencei, }), }
- rocket
- = .{ .name = "rocket", .llvm_name = "rocket", .features = featureSet(&[_]Feature{}), }
- rocket_rv32
- = .{ .name = "rocket_rv32", .llvm_name = "rocket-rv32", .features = featureSet(&[_]Feature{ .@"32bit", .i, .zicsr, .zifencei, }), }
- rocket_rv64
- = .{ .name = "rocket_rv64", .llvm_name = "rocket-rv64", .features = featureSet(&[_]Feature{ .@"64bit", .i, .zicsr, .zifencei, }), }
- rp2350_hazard3
- = .{ .name = "rp2350_hazard3", .llvm_name = "rp2350-hazard3", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .i, .m, .zba, .zbb, .zbkb, .zbs, .zcb, .zcmp, .zicsr, .zifencei, }), }
- sifive_7_series
- = .{ .name = "sifive_7_series", .llvm_name = "sifive-7-series", .features = featureSet(&[_]Feature{ .no_default_unroll, .short_forward_branch_opt, .use_postra_scheduler, }), }
- sifive_e20
- = .{ .name = "sifive_e20", .llvm_name = "sifive-e20", .features = featureSet(&[_]Feature{ .@"32bit", .c, .i, .m, .zicsr, .zifencei, }), }
- sifive_e21
- = .{ .name = "sifive_e21", .llvm_name = "sifive-e21", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .i, .m, .zicsr, .zifencei, }), }
- sifive_e24
- = .{ .name = "sifive_e24", .llvm_name = "sifive-e24", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .f, .i, .m, .zifencei, }), }
- sifive_e31
- = .{ .name = "sifive_e31", .llvm_name = "sifive-e31", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .i, .m, .zicsr, .zifencei, }), }
- sifive_e34
- = .{ .name = "sifive_e34", .llvm_name = "sifive-e34", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .f, .i, .m, .zifencei, }), }
- sifive_e76
- = .{ .name = "sifive_e76", .llvm_name = "sifive-e76", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .f, .i, .m, .no_default_unroll, .short_forward_branch_opt, .use_postra_scheduler, .zifencei, }), }
- sifive_p450
- = .{ .name = "sifive_p450", .llvm_name = "sifive-p450", .features = featureSet(&[_]Feature{ .@"64bit", .a, .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, .d, .i, .lui_addi_fusion, .m, .no_default_unroll, .unaligned_scalar_mem, .unaligned_vector_mem, .use_postra_scheduler, .za64rs, .zfhmin, .zic64b, .zicbom, .zicbop, .zicboz, .ziccamoa, .ziccif, .zicclsm, .ziccrse, .zicntr, .zifencei, .zihintntl, .zihintpause, .zihpm, .zkt, }), }
- sifive_p470
- = .{ .name = "sifive_p470", .llvm_name = "sifive-p470", .features = featureSet(&[_]Feature{ .@"64bit", .a, .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, .i, .lui_addi_fusion, .m, .no_default_unroll, .no_sink_splat_operands, .unaligned_scalar_mem, .unaligned_vector_mem, .use_postra_scheduler, .v, .vxrm_pipeline_flush, .xsifivecdiscarddlone, .xsifivecflushdlone, .za64rs, .zfhmin, .zic64b, .zicbom, .zicbop, .zicboz, .ziccamoa, .ziccif, .zicclsm, .ziccrse, .zicntr, .zifencei, .zihintntl, .zihintpause, .zihpm, .zkt, .zvbb, .zvknc, .zvkng, .zvksc, .zvksg, }), }
- sifive_p550
- = .{ .name = "sifive_p550", .llvm_name = "sifive-p550", .features = featureSet(&[_]Feature{ .@"64bit", .a, .auipc_addi_fusion, .c, .conditional_cmv_fusion, .d, .i, .lui_addi_fusion, .m, .no_default_unroll, .use_postra_scheduler, .zba, .zbb, .zifencei, }), }
- sifive_p670
- = .{ .name = "sifive_p670", .llvm_name = "sifive-p670", .features = featureSet(&[_]Feature{ .@"64bit", .a, .auipc_addi_fusion, .b, .c, .conditional_cmv_fusion, .i, .lui_addi_fusion, .m, .no_default_unroll, .no_sink_splat_operands, .unaligned_scalar_mem, .unaligned_vector_mem, .use_postra_scheduler, .v, .vxrm_pipeline_flush, .za64rs, .zfhmin, .zic64b, .zicbom, .zicbop, .zicboz, .ziccamoa, .ziccif, .zicclsm, .ziccrse, .zicntr, .zifencei, .zihintntl, .zihintpause, .zihpm, .zkt, .zvbb, .zvknc, .zvkng, .zvksc, .zvksg, }), }
- sifive_s21
- = .{ .name = "sifive_s21", .llvm_name = "sifive-s21", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .i, .m, .zicsr, .zifencei, }), }
- sifive_s51
- = .{ .name = "sifive_s51", .llvm_name = "sifive-s51", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .i, .m, .zicsr, .zifencei, }), }
- sifive_s54
- = .{ .name = "sifive_s54", .llvm_name = "sifive-s54", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .zifencei, }), }
- sifive_s76
- = .{ .name = "sifive_s76", .llvm_name = "sifive-s76", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .no_default_unroll, .short_forward_branch_opt, .use_postra_scheduler, .zifencei, .zihintpause, }), }
- sifive_u54
- = .{ .name = "sifive_u54", .llvm_name = "sifive-u54", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .zifencei, }), }
- sifive_u74
- = .{ .name = "sifive_u74", .llvm_name = "sifive-u74", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .no_default_unroll, .short_forward_branch_opt, .use_postra_scheduler, .zifencei, }), }
- sifive_x280
- = .{ .name = "sifive_x280", .llvm_name = "sifive-x280", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .dlen_factor_2, .i, .m, .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_zero_stride_load, .short_forward_branch_opt, .use_postra_scheduler, .v, .zba, .zbb, .zfh, .zifencei, .zvfh, .zvl512b, }), }
- spacemit_x60
- = .{ .name = "spacemit_x60", .llvm_name = "spacemit-x60", .features = featureSet(&[_]Feature{ .@"64bit", .a, .b, .c, .dlen_factor_2, .i, .m, .optimized_nf2_segment_load_store, .optimized_nf3_segment_load_store, .optimized_nf4_segment_load_store, .ssccptr, .sscofpmf, .sscounterenw, .sstc, .sstvala, .sstvecd, .svade, .svbare, .svinval, .svnapot, .svpbmt, .unaligned_scalar_mem, .v, .vxrm_pipeline_flush, .za64rs, .zbc, .zbkc, .zfh, .zic64b, .zicbom, .zicbop, .zicboz, .ziccamoa, .ziccif, .zicclsm, .ziccrse, .zicntr, .zicond, .zifencei, .zihintpause, .zihpm, .zkt, .zvfh, .zvkt, .zvl256b, }), }
- syntacore_scr1_base
- = .{ .name = "syntacore_scr1_base", .llvm_name = "syntacore-scr1-base", .features = featureSet(&[_]Feature{ .@"32bit", .c, .i, .no_default_unroll, .zicsr, .zifencei, }), }
- syntacore_scr1_max
- = .{ .name = "syntacore_scr1_max", .llvm_name = "syntacore-scr1-max", .features = featureSet(&[_]Feature{ .@"32bit", .c, .i, .m, .no_default_unroll, .zicsr, .zifencei, }), }
- syntacore_scr3_rv32
- = .{ .name = "syntacore_scr3_rv32", .llvm_name = "syntacore-scr3-rv32", .features = featureSet(&[_]Feature{ .@"32bit", .c, .i, .m, .no_default_unroll, .use_postra_scheduler, .zicsr, .zifencei, }), }
- syntacore_scr3_rv64
- = .{ .name = "syntacore_scr3_rv64", .llvm_name = "syntacore-scr3-rv64", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .i, .m, .no_default_unroll, .use_postra_scheduler, .zicsr, .zifencei, }), }
- syntacore_scr4_rv32
- = .{ .name = "syntacore_scr4_rv32", .llvm_name = "syntacore-scr4-rv32", .features = featureSet(&[_]Feature{ .@"32bit", .c, .d, .i, .m, .no_default_unroll, .use_postra_scheduler, .zifencei, }), }
- syntacore_scr4_rv64
- = .{ .name = "syntacore_scr4_rv64", .llvm_name = "syntacore-scr4-rv64", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .no_default_unroll, .use_postra_scheduler, .zifencei, }), }
- syntacore_scr5_rv32
- = .{ .name = "syntacore_scr5_rv32", .llvm_name = "syntacore-scr5-rv32", .features = featureSet(&[_]Feature{ .@"32bit", .a, .c, .d, .i, .m, .no_default_unroll, .use_postra_scheduler, .zifencei, }), }
- syntacore_scr5_rv64
- = .{ .name = "syntacore_scr5_rv64", .llvm_name = "syntacore-scr5-rv64", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .no_default_unroll, .use_postra_scheduler, .zifencei, }), }
- syntacore_scr7
- = .{ .name = "syntacore_scr7", .llvm_name = "syntacore-scr7", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .i, .m, .no_default_unroll, .use_postra_scheduler, .v, .zba, .zbb, .zbc, .zbs, .zifencei, .zkn, }), }
- tt_ascalon_d8
- = .{ .name = "tt_ascalon_d8", .llvm_name = "tt-ascalon-d8", .features = featureSet(&[_]Feature{ .@"64bit", .a, .b, .c, .i, .m, .no_default_unroll, .optimized_zero_stride_load, .sha, .smaia, .ssaia, .ssccptr, .sscofpmf, .sscounterenw, .ssnpm, .ssstrict, .sstc, .sstvala, .sstvecd, .ssu64xl, .supm, .svade, .svbare, .svinval, .svnapot, .svpbmt, .unaligned_scalar_mem, .unaligned_vector_mem, .use_postra_scheduler, .v, .za64rs, .zawrs, .zcb, .zcmop, .zfa, .zfh, .zic64b, .zicbom, .zicbop, .zicboz, .ziccamoa, .ziccif, .zicclsm, .ziccrse, .zicntr, .zicond, .zifencei, .zihintntl, .zihintpause, .zihpm, .zimop, .zkt, .zvbb, .zvbc, .zvfbfwma, .zvfh, .zvkng, .zvl256b, }), }
- veyron_v1
- = .{ .name = "veyron_v1", .llvm_name = "veyron-v1", .features = featureSet(&[_]Feature{ .@"64bit", .a, .auipc_addi_fusion, .c, .d, .i, .ld_add_fusion, .lui_addi_fusion, .m, .shifted_zextw_fusion, .ventana_veyron, .xventanacondops, .zba, .zbb, .zbc, .zbs, .zexth_fusion, .zextw_fusion, .zicbom, .zicbop, .zicboz, .zicntr, .zifencei, .zihintpause, .zihpm, }), }
- xiangshan_nanhu
- = .{ .name = "xiangshan_nanhu", .llvm_name = "xiangshan-nanhu", .features = featureSet(&[_]Feature{ .@"64bit", .a, .c, .d, .i, .m, .no_default_unroll, .shifted_zextw_fusion, .svinval, .zba, .zbb, .zbc, .zbs, .zexth_fusion, .zextw_fusion, .zicbom, .zicboz, .zifencei, .zkn, .zksed, .zksh, }), }