DoxigAlpha

tt_ascalon_d8

Source

Implementation

#
pub const tt_ascalon_d8: CpuModel = .{
    .name = "tt_ascalon_d8",
    .llvm_name = "tt-ascalon-d8",
    .features = featureSet(&[_]Feature{
        .@"64bit",
        .a,
        .b,
        .c,
        .i,
        .m,
        .no_default_unroll,
        .optimized_zero_stride_load,
        .sha,
        .smaia,
        .ssaia,
        .ssccptr,
        .sscofpmf,
        .sscounterenw,
        .ssnpm,
        .ssstrict,
        .sstc,
        .sstvala,
        .sstvecd,
        .ssu64xl,
        .supm,
        .svade,
        .svbare,
        .svinval,
        .svnapot,
        .svpbmt,
        .unaligned_scalar_mem,
        .unaligned_vector_mem,
        .use_postra_scheduler,
        .v,
        .za64rs,
        .zawrs,
        .zcb,
        .zcmop,
        .zfa,
        .zfh,
        .zic64b,
        .zicbom,
        .zicbop,
        .zicboz,
        .ziccamoa,
        .ziccif,
        .zicclsm,
        .ziccrse,
        .zicntr,
        .zicond,
        .zifencei,
        .zihintntl,
        .zihintpause,
        .zihpm,
        .zimop,
        .zkt,
        .zvbb,
        .zvbc,
        .zvfbfwma,
        .zvfh,
        .zvkng,
        .zvl256b,
    }),
}